1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a test apparatus for testing a semiconductor device, and a method thereof.
2. Description of the Related Art
Electronic appliances which are produced in these days may be designed to perform a smart operation in order to meet the needs of consumer. To implement this operation, various semiconductor chips such as a microprocessor, a networking chip, a memory, or the like are provided in the electronic appliances, and a secure and fast communication between the semiconductor chips in the electronic appliances may be more important due to complex and diverse trends of the electric appliances.
A System on Chip (SoC) technique is emerging that a plurality of semiconductor chips are organically connected and act as a single chip. In the SoC technique, a microprocessor, a digital processor, a memory, a baseband chip and the like are integrated in a single chip so that the single chip itself may function as a system. The SoC technique may have many advantages in terms of system cost and size of circuits, and the SoC technique may be expanding throughout an Information Technology (IT) industry as well as a semiconductor industry due to those advantages.
In the SoC technique, a memory and a non-memory required for a system are integrated in a single chip. A distinction between companies for manufacturing, production, and design of the SoC is becoming ambiguous, and thus the overall technical and market competition is getting fierce. In particular, since the SOC technique essentially requires a nanometer-scale deep-submicron process technology and a software technology, a competition to secure those technologies is expected to become more intense.
Meanwhile, due to a development of a semiconductor manufacturing technology and a design technology, high-performance products are possible to be produced. At this time, to test circuits inside a SoC, additional configurations are required as follows.
First, the existing test equipment may not be used in the SoC technology since concerns such as noise, signal delay, interference, and the like become important due to an ultra-fine process. Accordingly, a cost to purchase a new test apparatus and a time for developing the desired test may be required. Further, it may be difficult to test the SoC since it may be difficult to acquire interconnections required for a test between an input/output of the SoC between an input/output of core. In other words, plural cores are built inside the SoC but it may be difficult to separately provide each core with a respective pin for the test. Thus, a test apparatus and a test method are required to test the plural cores provided inside the SoC by using minimal test pins.
In the end, because it may be difficult to acquire additional pins required for testing the plural cores, and to couple an input/output of the SoC with inputs/outputs of the plural cores, a test apparatus for testing the SoC requires a unique test structure.
Meanwhile, a plurality of cores are provided in the SoC, and the cores are coupled to each other by a plurality of connecting lines. In the conventional SoC, it may be enough to test the SoC by testing static faults such as a stuck-at fault, an open-net fault, a shorted-net fault, or the like since reliability of a data transfer is only checked regardless of checking a speed during testing the connecting lines. However, in case of an SoC operating at a high speed, an additional test operation may require since a signal delay of the connecting lines causes the entire SoC to malfunction.